Power-on-Package vertical and lateral power delivery

Vicor Power-on-Package

Redefining 48V to PoL regulation for high-power processors and AI ASICs See it in action

Advantages of a new approach to power delivery

By overcoming the obstacles imposed on high power processors by high current delivery through the “last inch,” Vicor Power-on-Package technology does more than just improve performance and simplify motherboard design. It enables processors to achieve previously unattainable performance levels that are necessary to fulfill the promise of high-performance applications such as Artificial Intelligence.

Benefits of Power-on-Package

Higher peak and average current delivery >1000 Amps

Reduces motherboard copper and processor interconnect resistances by up to 50X

Reduces processor power pin count by >10X

Enabling processor performance previously unachievable for advanced applications

Big data mining

Artificial Intelligence

Machine learning

Autonomous vehicles

In response to ever-increasing demands within the cloud for high-performance applications, such as big data mining and artificial intelligence with its machine learning and deep learning applications, processor operating currents have risen to many hundreds of amperes. The remaining short distance PDN to the processor – the “last inch” – consisting of the motherboard power plane and interconnects within the processor socket, has become a limiting factor in processor performance and total system efficiency.

Progression of Vicor customer GPU/CPU peak current requirements

Meeting the challenge that conventional multiphase point-of-load voltage regulators cannot

Conventional multiphase VRs limit a high-power processor's full running potential

Low density prohibits close proximity to processor

Density challenge increases with higher currents

Additional phases for higher currents creates phase imbalance

High switching frequency noise

Power distribution loss from the VR to the processor, the last inch

Vicor technology eliminates the “last inch”

Factorized Power Architecture (FPA) replaces conventional multiphase regulators and achieves higher density and power system efficiency

FPA factorizes power conversion into separate regulation and transformation functions that can be individually optimized to maximize performance. The regulation module can be placed at any location on the motherboard while the critical current delivery module the current multiplier is optimized for density, efficiency and low noise and can be placed in extremely close proximity to the processor. Current multipliers are capable of delivering a high current of greater than 1000 Amps and enable a 50X reduction in PDN resistance. Depending on processor currents, Vicor offers both lateral and vertical factorized power options.

Factorized power regulation and transformation stages

High-current multiplication next to the processor

Power-on-Package solutions

Lateral Power Delivery (LPD)

High-current delivery is provided via MCM (Modular Current Multiplier) modules that are placed adjacent to the processor either on the motherboard or on the processor substrate. Placement of MCMs on the substrate minimizes PDN losses and reduces the number of processor substrate BGA pins required for power. LPD is designed to support the power delivery demands and unique form factor of OCP Accelerator Module (OAM) cards and custom AI accelerator cards.

Vicor Power-on-Package Lateral Power Delivery

Vertical Power Delivery (VPD)

For extremely high processor currents, VPD reduces PDN resistance by a further 10X over LPD by placing the current multiplier module directly underneath the processor. Delivering power vertically has the added advantage of opening up the topside PCB board area for high speed I/O and memory. VPD utilizes similar current multipliers to the Vicor LPD solution but integrates the high-frequency bypass capacitance typically placed beneath the processor into the gearbox package attached to the MCM. The gearbox also enables the necessary change in pitch from the MCM’s output pins to the processor’s power pins and its output power pins are also matched to the power map of the processor or ASIC to maximize performance.